According to a liquid crystal display device, a shift register, which sequentially drives pixels disposed in an array, is employed in a scanning signal line driving circuit and a data signal line driving circuit. Such a liquid crystal display device further includes so-called buffers, each of which outputs an amplified signal in a broad sense with a low output impedance, such as (i) a level shifter which carries out a level conversion with respect to a supply voltage and (ii) an amplifying circuit which outputs an inputted signal as it is. In a case where the shift register and the buffer are constituted by CMOS transistors, both of a process of forming a p-channel and a process of forming an n-channel are necessary. This complicates a manufacturing process of the liquid crystal display device. In view of the circumstances, it is preferable that the manufacturing process is simplified as follows. That is, it is preferable that each of the shift register and the buffer be constituted by transistors having an identical conductivity type, i.e., transistors having a unipolar channel (e.g. merely p-channel). For example, Patent Literature 1 discloses such a shift register constituted by transistors having a unipolar channel.
FIG. 32 is a circuit diagram illustrating a switch constituting the shift register of Patent Literature 1. FIG. 33 is a timing chart showing waveforms of respective various signals in the switch. The switch is constituted by a PMOS transistor QpA and a PMOS transistor QpB. A pulse signal Sin is supplied to a drain terminal of the PMOS transistor QpA, a pulse signal Sout is outputted from a source terminal of the PMOS transistor QpA, and a control signal D is supplied to a gate terminal of the PMOS transistor QpA via the PMOS transistor QpB. A voltage VSS of low level is supplied to a gate of the PMOS transistor QpB.
In a case where the pulse signal Sin has a high level while the control signal D is having a low level, the PMOS transistor QpB turns ON. This pulls down a voltage of the gate (node N) of the PMOS transistor QpA up to (VSS+|Vth|).
Under the circumstances, in a case where a pulse signal Sin of low level is supplied to the drain terminal of the PMOS transistor QpA (see (A) of FIG. 33), electric charge due to a parasitic capacitance between the drain terminal and the gate terminal of the PMOS transistor QpA cause a rapid decline in voltage of the node N. In a case where the voltage of the node N goes below (VSS+|Vth|), the PMOS transistor QpB turns OFF. This causes the node N to be in a floating state. Thus, the electric charge due to the parasitic capacitance is preserved. As a result, in a case where the pulse signal Sin has a voltage VSS, the voltage of the node N becomes smaller than the voltage VSS (see (B) of FIG. 33).
In a case where such a bootstrap operation causes the drain of the PMOS transistor QpA to be reduced to the voltage VSS, the gate terminal is driven by a voltage lower than the voltage VSS due to the electric charge caused by the parasitic capacitance between the gate and the drain. This causes the PMOS transistor QpA to maintain its ON state. As a result, a voltage that is substantially the same as the voltage VSS supplied to the drain terminal is outputted from the source terminal of the PMOS transistor QpA (see (C) of FIG. 33). That is, a voltage of a pulse signal which passes through the PMOS transistor QpA is reduced to the voltage VSS during a pulse period.
According to the circuit configuration of the switch shown in FIG. 32, it is possible to cause a voltage of a pulse signal, which has passed through the switch, to be reduced to the voltage VSS of low level (i) without using a voltage lower than the voltage VSS of low level and (ii) with a simple circuit configuration in which the transistors having an identical conductivity type are employed. As such, such a switch can be suitably used in each section of a liquid crystal display device.